1. Field of the Invention
The present invention relates to a semiconductor test apparatus for testing the logic characteristics of a semiconductor device.
2. Description of the Related Art
An essential portion of a conventional semiconductor test apparatus is shown in FIG. 3. Logical decision sections 1a to 1e each are correspondingly connected to a plurality of output pins 2a to 2e of a semiconductor device 2 to be tested. Each of the logical decision sections 1a to 1e has a high-level output comparator 3a and a low-level output comparator 3b which are connected to corresponding output pins of the semiconductor device 2, flip flops 5a and 5b are respectively connected to these comparators 3a and 3b, an OR circuit 6 is connected to the flip flops 5a and 5b, and a comparison circuit 7 is connected to the OR circuit 6. The output of the comparison circuit 7 of each of the logical decision sections 1a to 1e is connected to an OR circuit 8.
Next, the operation of the apparatus shown in FIG. 3 will be explained. The output from each of the output pins 2a to 2e of the semiconductor device 2 is output to the comparators 3a and 3b of the logical decision sections 1a to 1e. If the output from the output pins 2a to 2e is higher than a predefined value V.sub.oH which has been preset in the high-level output comparator 3a, the outputs from the comparators 3a and 3b both become high level outputs. Conversely, if that output is lower than a predefined value V.sub.oL which has been preset in the low-level output comparator 3b, the outputs from the comparators 3a and 3b both become low level outputs. These outputs from the comparators 3a and 3b are retained in the flip flops 5a and 5b, respectively, in accordance with a strobe signal S.sub.sT generated at a preset time, and then input to the comparison circuit 7 through the OR circuit 6. An expected level indicating what the output level from the corresponding output pins of the semiconductor device 2 should be at the time when a strobe signal S.sub.sT is generated is stored beforehand in the comparison circuit 7. The comparison circuit 7 compares the output level of the OR circuit 6 with the expected level, and outputs a low-level signal if these levels match each other and outputs a high-level signal if these levels do not match.
Signals output from the comparison circuit 7 of each of the logical decision sections 1a to 1e are input to the OR circuit 8. When all the output levels of the output pins 2a to 2e of the semiconductor device 2 match the expected levels, a low-level output is obtained from the OR circuit 8. If at least one of the output levels differs from the expected level, a high-level output is obtained.
The testing of the semiconductor device 2 has been performed in the above way.
FIG. 4 shows a semiconductor device 20 with a 4-bit A/D conversion function and a function of retaining its digital values. An analog value input to an analog waveform input pin 9 is converted to a digital value by means of an A/D converter 10. That digital value is retained in a latch circuit 12 at the time when a trigger is input to a trigger input pin 11. For example, when an analog value of 4 V is input to the input pin 9 at trigger input time, data of bits 0 to 3 output from output pins 20a to 20d become low level, low level, high level, and low level, respectively. Thus, 0100.sub.2, which is a binary representation of 4.sub.10 in the decimal representation, is the expected output of the semiconductor device 20. Consequently, if data 0100.sub.2 is output from the semiconductor device 20 in response to the above trigger input when the testing of the semiconductor device 20 is carried out by using the test apparatus shown in FIG. 3, the output of the OR circuit 8 becomes a low level output, which indicates that the operation of the semiconductor device 20 is normal.
However, if the precision of the A/D converter 10 contained in the semiconductor device 20 is assumed to be .+-.2LSB, it is necessary that this semiconductor device 20 be determined to be normal even when the output from the semiconductor device 20 is 0010.sub.2 (2.sub.10), 0011.sub.2 (3.sub.10), 0101.sub.2 (5.sub.10), and 0110.sub.2 (6.sub.10) in addition to 0100.sub.2 (4.sub.10). However, in the conventional test apparatus shown in FIG. 3, only one of a high or a low level can be set for an expected level from each of the output pins of the semiconductor device 2 at strobe signal S.sub.sT input time. For this reason, as in the semiconductor device 20 shown in FIG. 4, when whether the device 20 is nondefective or defective is determined by a combination of the output levels from a plurality of output pins 20a to 20d, a plurality of tests are carried out by varying expected values consisting of a combination of expected levels for the respective output pins 20a to 20d. When at least one output block of data matches the expected value in the plurality of these tests, the semiconductor device is determined to be nondefective.
The flowchart of the testing in this case is shown in FIG. 5. First, a minimum 0010.sub.2 from among a plurality of expected values is assumed to be an initial expected value DATA in step S1. This expected value DATA is set in a test apparatus in step S2, and the test is performed in step S3. In step S4, it is determined whether or not the result of the test shows "defective". When it is not defective, a flag is set to 1 in step S5, then in step S6 the number of tests is checked. If the result of the determination in step S4 is "defective", the process proceeds directly to step S6. If it is determined in step S6 that this is not a fifth test, the expected value DATA is incremented by 1 in step S7. For example, if the expected value DATA up to the present time is 0010.sub.2, this value is modified to 0011.sub.2, and the process returns to step S2, and steps S2 to S6 are repeated again.
When five tests are completed in the above way, it is checked in step S8 whether or not the flag is 1. If the flag is 1, then it is determined in step S9 that the semiconductor device 20 is nondefective; if not 1, it is determined in step S10 that the semiconductor device 20 is defective.
From the above procedure, when the output of the semiconductor device 20 is from 0010.sub.2 (2.sub.10) to 0110.sub.2 (6.sub.10), the semiconductor device 20 is determined to be nondefective.
As described above, in the conventional semiconductor test apparatus, when expected values of a wide range exist from a combination of each level of a plurality of output pins of a semiconductor device, a plurality of similar tests must be carried out. That is, a problem exists in that testing requires a long period of time.